System architecture for multi-technology testbench-on-a-chip

A Hodge; R Newcomb; M Zaghloul; O Tigli

doi:10.1109/ISCAS.2002.1011458

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Conference proceeding

System architecture for multi-technology testbench-on-a-chip

A Hodge, R Newcomb, M Zaghloul and O Tigli

2002 IEEE International Symposium on Circuits and Systems (ISCAS), Vol.2, pp.II-II

2002

DOI: https://doi.org/10.1109/ISCAS.2002.1011458

Abstract

Application specific integrated circuits

Built-in self-test

Circuit testing

Circuits and systems

Computer architecture

Educational institutions

Integrated circuit technology

Metrology

System testing

System-on-a-chip

The architecture for a multi-technology testbench on a chip is presented for functional testing of mixed signal devices. The technologies tested by this system-on-a-chip (SoC) include op amps, biosensors, and smart signal processing of analog/digital multiplexers. This paper focuses on describing the architecture of the testbench on a chip as well as the results obtained from testing integral components of the fabricated device. The objective of this research is to uncover key metrology infrastructure issues needed for developing the design reuse approach for multi-technology system-on-a-chip (SoC) devices.

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Details

Title: System architecture for multi-technology testbench-on-a-chip
Creators: A Hodge - Naval Res. Lab., Washington, DC, USA
R Newcomb
M Zaghloul
O Tigli
Publication Details: 2002 IEEE International Symposium on Circuits and Systems (ISCAS), Vol.2, pp.II-II
Publisher: IEEE
Academic Unit: College of Engineering; CoE - Electrical & Computer Engineering
Language: English
Resource Type: Conference proceeding
Record Identifier: 991031613085502976